octal d?type flip?flop with 3?state output the mc74vhc374 is an advanced high speed cmos octal flip ? flip with 3 ? state output fabricated with silicon gate cmos technology. it achieves high speed operation similar to equivalent bipolar schottky ttl while maintaining cmos low power dissipation. this 8 ? bit d ? type flip ? flop is controlled by a clock input and an output enable input. when the output enable input is high, the eight outputs are in a high impedance state. the internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. the inputs tolerate voltages up to 7v , allowing the interface of 5v systems to 3v systems. ? high speed: f max = 185mhz (typ) at v cc = 5v ? low power dissipation: i cc = 4 a (max) at t a = 25 c ? high noise immunity: v nih = v nil = 28% v cc ? power down protection provided on inputs ? balanced propagation delays ? designed for 2v to 5.5v operating range ? low noise: v olp = 0.9v (max) ? pin and function compatible with other standard logic families ? latchup performance exceeds 300ma ? esd performance: hbm > 2000v; machine model > 200v ? chip complexity: 266 fets or 66.5 equivalent gates these devices are available in pb ? free package(s). specifications herein apply to both standard and pb ? free devices. please see our website at www.onsemi.com for specific pb ? free orderable part numbers, or contact your local on semiconductor sales office or representative. on semiconductor ? semiconductor components industries, llc, 2006 march, 2006 ? rev. 5 1 publication order number: mc74vhc374/d mc74vhc374 dw suffix 20 ? lead soic wide package case 751d ? 05 ordering information mc74vhcxxxdw mc74vhcxxxdt mc74vhcxxxm soic wide tssop soic eiaj dt suffix 20 ? lead tssop package case 948e ? 02 m suffix 20 ? lead soic eiaj package case 967 ? 01
http://onsemi.com 2 figure 1. logic diagram data inputs d0 d1 d2 d3 d4 d5 d6 d7 18 17 14 13 8 7 4 3 1 oe 19 q0 q1 q2 q3 q4 q5 q6 q7 16 15 12 9 6 5 2 noninverting outputs 11 cp oe cp q l l l h l, h, x h l no change z inputs output function table d h l x x figure 2. pin assignment q2 d1 d0 q0 oe gnd q3 d3 d2 q1 5 4 3 2 1 10 9 8 7 6 14 15 16 17 18 19 20 11 12 13 q6 d6 d7 q7 v cc cp q4 d4 d5 q5
http://onsemi.com 3 ??????????????????????? ??????????????????????? ???? ???? ?????????????? ?????????????? ????? ????? ??? ??? ???? ???? v cc ?????????????? ?????????????? ????? ????? ??? ??? ???? ???? ?????????????? ?????????????? ????? ????? ??? ??? ???? ???? ?????????????? ?????????????? ????? ????? ??? ??? ???? ???? ?????????????? ?????????????? ????? ????? ? 20 ??? ??? ???? ???? ?????????????? ?????????????? ????? ????? 20 ??? ??? ???? ???? ?????????????? ?????????????? ????? ????? 25 ??? ??? ???? ???? ?????????????? ?????????????? ????? ????? 75 ??? ??? ???? ? ?? ? ???? p d ?????????????? ? ???????????? ? ?????????????? power dissipation in still air, soic packages? tssop package? ????? ? ??? ? ????? 500 450 ??? ? ? ? ??? mw ???? ???? ?????????????? ?????????????? ????? ????? ??? ??? c * absolute maximum continuous ratings are those values beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolute ? maximum ? rated conditions is not implied. ?derating ? soic packages: ? 7 mw/ c from 65 to 125 c tssop package: ? 6.1 mw/ c from 65 to 125 c recommended operating conditions ???? ???? ??????????????? ??????????????? ??? ??? ?? ?? ??? ??? ???? ???? v cc ??????????????? ??????????????? ??? ??? ?? ?? ??? ??? ???? ???? ??????????????? ??????????????? ??? ??? ?? ?? ??? ??? ???? ???? ??????????????? ??????????????? ??? ??? ?? ?? ??? ??? ???? ???? ??????????????? ??????????????? ??? ??? ? 40 ?? ?? ??? ??? c ???? ? ?? ? ???? t r , t f ??????????????? ? ????????????? ? ??????????????? input rise and fall time v cc = 3.3v v cc = 5.0v ??? ? ? ? ??? 0 0 ?? ?? ?? ??? ? ? ? ??? ns/v ????????????????????????????????? dc electrical characteristics ???? ? ?? ? ???? symbol ??????? ? ????? ? ??????? parameter ??????? ? ????? ? ??????? test conditions ??? ? ? ? ??? v cc v ????????? ????????? c ??????? ??????? ? 40 to 85 c ?? ?? ?? ???? ???? ??? ??? ???? ???? ???? ???? ???? ???? ???? ? ?? ? ? ?? ? ???? v ih ??????? ? ????? ? ? ????? ? ??????? minimum high ? level input voltage ??????? ? ????? ? ? ????? ? ??????? ??? ? ? ? ? ? ? ??? 2.0 3.0 to 5.5 ???? ? ?? ? ? ?? ? ???? 1.50 v cc x 0.7 ??? ? ? ? ? ? ? ??? ???? ? ?? ? ? ?? ? ???? ???? ? ?? ? ? ?? ? ???? 1.50 v cc x 0.7 ???? ? ?? ? ? ?? ? ???? ?? ?? ?? ?? v ???? ? ?? ? ???? v il ??????? ? ????? ? ??????? maximum low ? level input voltage ??????? ? ????? ? ??????? ??? ? ? ? ??? 2.0 3.0 to 5.5 ???? ? ?? ? ???? ??? ? ? ? ??? ???? ? ?? ? ???? 0.50 v cc x 0.3 ???? ? ?? ? ???? ???? ? ?? ? ???? 0.50 v cc x 0.3 ?? ?? ?? ???? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ???? v oh ??????? ? ????? ? ? ????? ? ? ????? ? ? ????? ? ??????? minimum high ? level output voltage ??????? ? ????? ? ??????? v in = v ih or v il i oh = ? 50 a ??? ? ? ? ??? 2.0 3.0 4.5 ???? ? ?? ? ???? 1.9 2.9 4.4 ??? ? ? ? ??? 2.0 3.0 4.5 ???? ? ?? ? ???? ???? ? ?? ? ???? 1.9 2.9 4.4 ???? ? ?? ? ???? ?? ?? ?? ?? ?? ?? v ??????? ? ????? ? ? ????? ? ??????? v in = v ih or v il i oh = ? 4ma i oh = ? 8ma ??? ? ? ? ? ? ? ??? 3.0 4.5 ???? ? ?? ? ? ?? ? ???? 2.58 3.94 ??? ? ? ? ? ? ? ??? ???? ? ?? ? ? ?? ? ???? ???? ? ?? ? ? ?? ? ???? 2.48 3.80 ???? ? ?? ? ? ?? ? ???? ???? ? ?? ? ? ?? ? ? ?? ? ???? v ol ??????? ? ????? ? ? ????? ? ? ????? ? ??????? maximum low ? level output voltage ??????? ? ????? ? ??????? v in = v ih or v il i ol = 50 a ??? ? ? ? ??? 2.0 3.0 4.5 ???? ? ?? ? ???? ??? ? ? ? ??? 0.0 0.0 0.0 ???? ? ?? ? ???? 0.1 0.1 0.1 ???? ? ?? ? ???? ???? ? ?? ? ???? 0.1 0.1 0.1 ?? ?? ?? ?? ?? ??????? ? ????? ? ??????? v in = v ih or v il i ol = 4ma i ol = 8ma ??? ? ? ? ??? 3.0 4.5 ???? ? ?? ? ???? ??? ? ? ? ??? ???? ? ?? ? ???? 0.36 0.36 ???? ? ?? ? ???? ???? ? ?? ? ???? 0.44 0.44 this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high ? impedance cir- cuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
http://onsemi.com 4 ????????????????????????????????? ????????????????????????????????? ?? ?? ??????? ??????? ? 40 to 85 c ????????? ????????? c ??? ??? ??????? ??????? ??????? ??????? ???? ???? ?? ?? ???? ???? ???? ???? ???? ???? ??? ??? ???? ???? ??? ??? ??????? ??????? ??????? ??????? ???? ???? ???? ? ?? ? ???? i in ??????? ? ????? ? ??????? maximum input leakage current ??????? ? ????? ? ??????? v in = 5.5v or gnd ??? ? ? ? ??? 0 to 5.5 ???? ? ?? ? ???? ??? ? ? ? ??? ???? ? ?? ? ???? 0.1 ???? ? ?? ? ???? ???? ? ?? ? ???? 1.0 ?? ?? ?? a ???? ? ?? ? ???? i oz ??????? ? ????? ? ??????? maximum three ? state leakage current ??????? ? ????? ? ??????? v in = v il or v ih v out = v cc or gnd ??? ? ? ? ??? 5.5 ???? ? ?? ? ???? ??? ? ? ? ??? ???? ? ?? ? ???? 0.25 ???? ? ?? ? ???? ???? ? ?? ? ???? 2.5 ?? ?? ?? a ???? ? ?? ? ???? i cc ??????? ? ????? ? ??????? maximum quiescent supply current ??????? ? ????? ? ??????? v in = v cc or gnd ??? ? ? ? ??? 5.5 ???? ? ?? ? ???? ??? ? ? ? ??? ???? ? ?? ? ???? 4.0 ???? ? ?? ? ???? ???? ? ?? ? ???? 40.0 ?? ?? ?? a ????????????????????????????????? ????????????????????????????????? ac electrical characteristics (input t r = t f = 3.0ns) ???? ? ?? ? ???? symbol ????????? ? ??????? ? ????????? parameter ???????? ? ?????? ? ???????? test conditions ????????? ????????? c ?????? ?????? ? 40 to 85 c ?? ?? ?? ???? ???? ??? ??? ???? ???? ??? ??? ???? ???? ???? ? ?? ? ? ?? ? ? ?? ? ???? f max ????????? ? ??????? ? ? ??????? ? ? ??????? ? ????????? maximum clock frequency (50% duty cycle) ???????? ? ?????? ? ???????? v cc = 3.3 0.3v c l = 15pf c l = 50pf ???? ? ?? ? ???? 80 55 ??? ? ? ? ??? 130 85 ???? ? ?? ? ???? ??? ? ? ? ??? 70 50 ???? ? ?? ? ???? ?? ?? ?? ?? ?? ns ???????? ? ?????? ? ???????? v cc = 5.0 0.5v c l = 15pf c l = 50pf ???? ? ?? ? ???? 130 85 ??? ? ? ? ??? 185 120 ???? ? ?? ? ???? ??? ? ? ? ??? 110 75 ???? ? ?? ? ???? ???? ? ?? ? ? ?? ? ???? t plh , t phl ????????? ? ??????? ? ? ??????? ? ????????? maximum propagation delay, cp to q ???????? ???????? 0.3v c l = 15pf c l = 50pf ???? ???? ??? ??? ???? ???? ??? ??? ???? ???? ?? ?? ?? ?? ???????? ? ?????? ? ???????? v cc = 5.0 0.5v c l = 15pf c l = 50pf ???? ? ?? ? ???? ??? ? ? ? ??? 5.4 6.9 ???? ? ?? ? ???? 8.1 10.1 ??? ? ? ? ??? 1.0 1.0 ???? ? ?? ? ???? 9.5 11.5 ???? ? ?? ? ? ?? ? ???? t pzl , t pzh ????????? ? ??????? ? ? ??????? ? ????????? output enable time, oe to q ???????? ? ?????? ? ???????? v cc = 3.3 0.3v c l = 15pf r l = 1k c l = 50pf ???? ? ?? ? ???? ??? ? ? ? ??? 7.1 9.6 ???? ? ?? ? ???? 11.0 14.5 ??? ? ? ? ??? 1.0 1.0 ???? ? ?? ? ???? 13.0 16.5 ?? ?? ?? ?? ???????? ???????? 0.5v c l = 15pf r l = 1k c l = 50pf ???? ???? ??? ??? ???? ???? ??? ??? ???? ???? ???? ? ?? ? ? ?? ? ? ?? ? ???? t plz , t phz ????????? ? ??????? ? ? ??????? ? ? ??????? ? ????????? output disable time, oe to q ???????? ? ?????? ? ???????? v cc = 3.3 0.3v c l = 50pf r l = 1k ???? ? ?? ? ???? ??? ? ? ? ??? 10.2 ???? ? ?? ? ???? 14.0 ??? ? ? ? ??? 1.0 ???? ? ?? ? ???? 16.0 ?? ?? ?? ?? ?? ???????? ? ?????? ? ???????? v cc = 5.0 0.5v c l = 50pf r l = 1k ???? ? ?? ? ???? ??? ? ? ? ??? 6.1 ???? ? ?? ? ???? 8.8 ??? ? ? ? ??? 1.0 ???? ? ?? ? ???? 10.0 ???? ? ?? ? ? ?? ? ???? t oslh , t oshl ????????? ? ??????? ? ? ??????? ? ????????? output to output skew ???????? ???????? 0.3v c l = 50pf (note 1) ???? ???? ??? ??? ???? ???? ??? ??? ???? ???? ?? ?? ???????? ? ?????? ? ???????? v cc = 5.0 0.5v c l = 50pf (note 1) ???? ? ?? ? ???? ??? ? ? ? ??? ???? ? ?? ? ???? 1.0 ??? ? ? ? ??? ???? ? ?? ? ???? 1.0 ?? ?? ?? ???? ???? ????????? ????????? ???????? ???????? ???? ???? ??? ??? ???? ???? ??? ??? ???? ???? ?? ?? ???? ? ?? ? ???? c out ????????? ? ??????? ? ????????? maximum three ? state output capacitance (output in high ? impedance state) ???????? ? ?????? ? ???????? ???? ? ?? ? ???? ??? ? ? ? ??? 6 ???? ? ?? ? ???? ??? ? ? ? ??? ???? ? ?? ? ???? ?? ?? ?? pf c pd power dissipation capacitance (note 2) typical @ 25 c, v cc = 5.0v pf 32 1. parameter guaranteed by design. t oslh = |t plhm ? t plhn |, t oshl = |t phlm ? t phln |. 2. c pd is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption with out load. average operating current can be obtained by the equation: i cc(opr ) = c pd v cc f in + i cc / 8 (per flip ? flop). c pd is used to determine the no ? load dynamic power consumption; p d = c pd v cc 2 f in + i cc v cc .
http://onsemi.com 5 noise characteristics (input t r = t f = 3.0ns, c l = 50pf, v cc = 5.0v) symbol parameter t a = 25 c unit typ max v olp quiet output maximum dynamic v ol 0.6 0.9 v v olv quiet output minimum dynamic v ol ? 0.6 ? 0.9 v v ihd minimum high level dynamic input voltage 3.5 v v ild maximum low level dynamic input voltage 1.5 v timing requirements (input t r = t f = 3.0ns) symbol parameter test conditions t a = 25 c t a = ? 40 to 85 c unit typ limit limit t w minimum pulse width, cp v cc = 3.3 0.3 v v cc = 5.0 0.5 v 5.0 5.0 5.5 5.0 ns t su minimum setup time, d to cp v cc = 3.3 0.3 v v cc = 5.0 0.5 v 4.5 3.0 4.5 3.0 ns t h minimum hold time, d to cp v cc = 3.3 0.3 v v cc = 5.0 0.5 v 2.0 2.0 2.0 2.0 ns t r , t f maximum input rise and fall times v cc = 3.3 0.3 v v cc = 5.0 0.5 v ns switching waveforms figure 3. v cc gnd 50% v cc 50% cp t plh t phl q t w 1/f max 50% 50% v cc 50% v cc oe q t pzl t plz t pzh t phz v cc gnd high impedance v ol +0.3v v oh ?0.3v high impedance 50% d cp v cc v cc gnd gnd valid t h t su 50% q figure 4. figure 5.
http://onsemi.com 6 test circuits figure 6. *includes all probe and jig capacitance c l * test point device under test output *includes all probe and jig capacitance c l * test point device under test output connect to v cc when testing t plz and t pzl . connect to gnd when testing t phz and t pzh . 1 k figure 7. figure 8. expanded logic diagram d0 3 dq c q0 2 d1 4 dq c q1 5 d2 7 dq c q2 6 d3 8 dq c q3 9 d4 13 dq c q4 12 d5 14 dq c q5 15 d6 17 dq c q6 16 d7 18 dq c q7 19 cp oe 11 1 figure 9. input equivalent circuit input
http://onsemi.com 7 outline dimensions case 751d ? 05 issue f dw suffix 20 1 11 10 b 20x h 10x c l 18x a1 a seating plane h x 45 e d m 0.25 m b m 0.25 s a s b t e t b a dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 12.65 12.95 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of b dimension at maximum material condition. soic case 948e ? 02 issue a tssop dim a min max min max inches 6.60 0.260 millimeters b 4.30 4.50 0.169 0.177 c 1.20 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.27 0.37 0.011 0.015 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ?w?. 110 11 20 pin 1 ident a b ? t ? 0.100 (0.004) c d g h section n ? n k k1 jj1 n n m f ? w ? seating plane ? v ? ? u ? s u m 0.10 (0.004) v s t 20x ref k l l/2 2x s u 0.15 (0.006) t detail e 0.25 (0.010) detail e 6.40 0.252 ??? ??? s u 0.15 (0.006) t dt suffix
http://onsemi.com 8 outline dimensions case 967 ? 01 issue o m suffix dim min max min max inches ??? 2.05 ??? 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 12.35 12.80 0.486 0.504 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 ??? 0.81 ??? 0.032 a 1 h e q 1 l e 10 0 10 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). h e a 1 l e q 1 c a z d e 20 110 11 b m 0.13 (0.005) e 0.10 (0.004) view p detail p m l a b c d e e l m z soic eiaj on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2 ? 9 ? 1 kamimeguro, meguro ? ku, tokyo, japan 153 ? 0051 phone : 81 ? 3 ? 5773 ? 3850 mc74vhc374/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082 ? 1312 usa phone : 480 ? 829 ? 7710 or 800 ? 344 ? 3860 toll free usa/canada fax : 480 ? 829 ? 7709 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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